Click here to return to the VHDL Reference Guide. (last edit: 24. september 2012)

Qualified Expression

Used to define the type of an expression where otherwise the type would be ambiguous.

Syntax

  {either}
  TypeName'(Expression)
  TypeName'Aggregate
    

Where

See Expression

Rules

The Expression or Aggregate must be compatible with the TypeName; a qualified expression is not a type conversion!

Tips

Use a qualified expression when the compiler gives an error indicating that the type of an expression is ambiguous. This can occur when calling overloaded functions and procedures (e.g. (1) and (2) below), and when constructing aggregates (e.g. (3) and (4) below).

Example

  subtype T is STD_LOGIC_VECTOR(1 to 2);
  ...
  if U > UNSIGNED'("10000000") then                     -- (1)
    WRITE (L, STRING'("Hello"));                        -- (2)
    V := (others => T'(others => '1')); -- (3)
    case T'(A, B) is                                    -- (4)
    

See Also

Aggregate, Expression, Type Conversion, TEXTIO